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description the cxd2027q/r are audio signal processors designed for dbs applications. these lsis perform all digital processing from qpsk demodulation to analog audio output on a single chip. features qpsk and pcm demodulators and dac output are configured on a single chip. descrambler interface according to the coatec system and skyport system . functions qpsk demodulator carrier, clock and data regeneration alc and vcxo adjustment-free pcm demodulator frame sync protection by correlation detection de-interleaving and descrambling bch error correction, range bit error correction audio data range control expansion from 10 to 14 bits in a mode upper bit majority correction in b mode control sign integration correction, chargeable flag integration correction by master frame synchronization interface output for external dac digital interface output 1-bit dac output quadruple oversampling filter digital de-emphasis circuit 1-bit stereo dac with 2nd-order ? format noise shaper s/n ratio : 90db (typ.) distortion : 0.011% (typ.) cpu interface ? 2 c bus descrambler interface coatec system, skyport system mute functions error occurrence frequency detection mute audio chargeable flag detection mute control sign (b7) detection mute structure silicon gate cmos ic applications tvs, vcrs with built-in bs tuners absolute maximum ratings (ta = 25?, vss = 0v) supply voltage v dd vss ?0.5 to +7.0 v input voltage v i vss ?0.5 to v dd + 0.5 v output voltage v o vss ?0.5 to v dd + 0.5 v storage temperature tstg ?5 to +150 ? operating conditions supply voltage v dd 4.75 to 5.25 v operating temperature topr ?0 to +75 ? ?1 cxd2027q/r e94808-st dbs audio signal processor sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxd2027q 64 pin qfp (plastic) cxd2027r 80 pin lqfp (plastic)
?2 cxd2027q/r data recovery frame sync de-scrambler bch decoder (63, 56) shifter & range bit bch (7, 3) alc signal generator master frame sync de-interleaver 4 kbit-ram 10 ? 14 bit data expand majority error correction mute signal generator control word integral correction 8th range bit integral correction clock generator carrier recovery system clock generator audio data interpolator digital filter de-enphasis dac1 dac2 audio interface digital interface i 2 c bus i/f timing generator clock recovery adc rt adin rb gr alco phaa m23i m23o phab mcki f256 bclk aud rno rpo lno lpo mute lrck datb data dato dsla nsyn biti dslb bito fram tx sasl sclk sda dtup cc1 ck2m mcko 4 5 6 7 8 9 11 12 13 14 15 25 28 38 35 32 43 44 45 46 47 48 50 51 54 56 57 58 67 64 65 66 71 73 76 77 block diagram note) pin numbers are for the cxd2027r.
?3 cxd2027q/r pin configuration 1 cxd2027q 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 v dd 5 m23o m23i phaa alco v ss 9 tst7 rt adin advd advs rb gr v ss 6 v ss 5 rno v dd 2 rpo v ss 4 tst1 v ss 3 lpo v dd 1 lno v ss 2 v ss 1 tst0 mrst v ss 0 bito biti dslb dsla datb data v dd 0 ck2m fram dato cc1 tx tst2 tst3 tst4 tst5 v dd 4 phab mcki mcko v ss 8 mute tst8 v ss 7 sclk sda v dd 3 nsyn dtup f256 bclk lrck aud tst6 sasl 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10111213141516171819
?4 cxd2027q/r pin configuration 2 cxd2027r 68 69 70 71 72 73 74 75 76 77 78 79 80 33 32 31 30 29 28 27 26 25 24 23 22 21 rt adin advd advs rb gr v dd 2 rpo v ss 4 tst1 v ss 3 lpo v dd 1 n.c. lno v ss 2 v ss 1 n.c. n.c. n.c. mrst v ss 0 bito biti dslb dsla datb data v dd 0 ck2m fram dato cc1 tx tst2 tst3 tst4 tst5 v dd 4 phab mcki mcko v ss 8 mute tst8 v ss 7 sclk sda v dd 3 nsyn dtup f256 bclk lrck aud tst6 n.c. 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 1 2 3 4 5 6 7 8 9 10111213141516171819 n.c. 20 40 39 38 37 36 35 34 n.c. n.c. sasl v ss 6 v ss 5 rno n.c. n.c. 41 61 62 63 64 65 66 67 v dd 5 m23o m23i phaa alco v ss 9 tst7 n.c. n.c. tst0 n.c. n.c. n.c. n.c.
?5 cxd2027q/r pin description 1 cxd2027q (64pin qfp) pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 tst0 mrst v ss digital bito biti dslb dsla datb data v dd digital ck2m fram dato cc1 tx tst2 tst3 tst4 tst5 v ss digital v ss d/a lno v dd d/a lpo v ss d/a tst1 v ss d/a rpo v dd d/a rno v ss d/a v ss digital sasl tst6 i i o i i i i i o o o o o i i i i o o i o o i i test pin; normally low master reset; h: normal operation; l: reset digital ground bit stream output after psk demodulation bit stream input after psk demodulation external descrambler pin external descrambler pin data input 2 after bch correction (for coatec) data input 1 after bch correction (for skyport) digital +5v power supply 2.048mhz clock output frame start bit flag data output after bch correction control sign first bit output digital format audio output test pin; normally low test pin; normally low test pin; normally low test pin; normally high digital ground analog ground lch d/a converter output analog +5v power supply lch d/a converter output analog ground test pin; normally low analog ground rch d/a converter output analog +5v power supply rch d/a converter output analog ground digital ground i 2 c bus slave address select (l: d4, h: d6) test pin; normally low internal pull down internal pull up ttl input ttl input ttl input ttl input ttl input internal pull down internal pull down internal pull down internal pull down internal pull down internal pull down symbol i/o pin description remarks
?6 cxd2027q/r 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 aud lrck bclk f256 dtup nsyn v dd digital sda sclk v ss digital tst8 mute v ss digital mcko mcki phab v dd digital v dd digital m23o m23i phaa alco v ss digital tst7 rt adin v dd a/d v ss a/d rb gr o o o o o o i i i i o i o o i o o i i i i i audio data output for external df/dac lr clock output for external df/dac bit clock output for external df/dac clock output for external df/dac ccup: control sign update flag / ded: bch 2 error detection asynchronous flag (h: asynchronous; l: synchronous) digital +5v power supply sda (i 2 c bus) scl (i 2 c bus) digital ground test pin; normally low external forced muting input digital ground mcki inversion output 24.576mhz clock input clock regeneration phase error data output digital +5v power supply digital +5v power supply m23i inversion output 22.909088mhz clock input carrier regeneration phase error data output alc a/d control output digital ground test pin; normally low a/d converter vrt input analog data input analog +5v power supply analog ground a/d converter vrb input; connect to analog ground a/d converter vgr input; connect to analog ground switched by i 2 c bus i 2 c bus compatible i 2 c bus compatible ttl input pin no. symbol i/o pin description remarks
?7 cxd2027q/r pin description 2 cxd2027r (80pin lqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 n.c. mrst v ss digital bito biti dslb dsla datb data v dd digital ck2m fram dato cc1 tx tst2 tst3 tst4 tst5 n.c. n.c. n.c. v ss digital v ss d/a lno n.c. v dd d/a lpo v ss d/a tst1 v ss d/a rpo v dd d/a n.c. i o i i i i i o o o o o i i i i o o i o non-connection master reset; h: normal operation; l: reset digital ground bit stream output after psk demodulation bit stream input after psk demodulation external descrambler pin external descrambler pin data input 2 after bch correction (for coatec) data input 1 after bch correction (for skyport) digital +5v power supply 2.048mhz clock output frame start bit flag data output after bch correction control sign first bit output digital format audio output test pin; normally low test pin; normally low test pin; normally low test pin; normally high non-connection non-connection non-connection digital ground analog ground lch dac output non-connection analog +5v power supply lch dac output analog ground test pin; normally low analog ground rch dac output analog +5v power supply non-connection internal pull up ttl input ttl input ttl input ttl input ttl input internal pull down internal pull down internal pull down internal pull down pin no. symbol i/o pin description remarks
?8 cxd2027q/r 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 rno v ss d/a v ss digital sasl n.c. n.c. n.c. tst6 aud lrck bclk f256 dtup nsyn v dd digital sda sclk v ss digital tst8 mute v ss digital mcko mcki phab v dd digital n.c. n.c. n.c. v dd digital m23o m23i phaa alco v ss digital n.c. tst7 o i i o o o o o o i i i i o i o o i o o i rch d/a converter output analog ground digital ground i 2 c bus slave address select (l: d4, h: d6) non-connection non-connection non-connection test pin; normally low audio data output for external df/dac lr clock output for external df/dac bit clock output for external df/dac clock output for external df/dac ccup: control sign update flag/ded: bch 2 error detection asynchronous flag (h: asynchronous; l: synchronous) digital +5v power supply sda (i 2 c bus) scl (i 2 c bus) digital ground test pin; normally low external forced muting input digital ground mcki inversion output 24.576mhz clock input clock regeneration phase error data output digital +5v power supply non-connection non-connection non-connection digital +5v power supply m23i inversion output 22.909088mhz clock input carrier regeneration phase error data output alc a/d control output digital ground non-connection test pin; normally low internal pull down internal pull down switched by i 2 c bus i 2 c bus compatible i 2 c bus compatible ttl input pin no. symbol i/o pin description remarks
?9 cxd2027q/r 71 72 73 74 75 76 77 78 79 80 rt n.c. adin v dd a/d v ss a/d rb gr tst0 n.c. n.c. i i i i i a/d converter vrt input non-connection analog data input analog +5v power supply analog ground a/d converter vrb input; connect to analog ground a/d converter vgr input; connect to analog ground a/d test pin; normally low non-connection non-connection internal pull down absolute maximum ratings (ta = 25?, vss = 0v) item supply voltage input voltage output voltage operating temperature storage temperature v dd v i v o topr tstg vss ?0.5 to +7.0 vss ?0.5 to v dd + 0.5 vss ?0.5 to v dd + 0.5 ?0 to +75 ?5 to +150 v v v ? ? symbol ratings unit i/o pin capacitance (v dd = v i = 0v, f = 1mhz) item input pin capacitance output pin capacitance input/output pin capacitance c in c out c i/o 9 10 11 11 10 pf * 1 * 2 * 3 * 4 * 5 symbol min. typ. max. unit corresponding pins * 1 input pins other than * 2 and * 3 * 2 sclk * 3 biti, dslb, dsla, datb, data, tst5 * 4 all output pins * 5 sda pin no. symbol i/o description remarks
?10 cxd2027q/r electrical characteristics [dc characteristics] (v dd = 5v 0.25v, vss = 0v, ta = ?0 to +75?) item power consumption input/output voltage input voltage input rise/fall time output voltage p d v i , v o v ih v il v ih v il vt + vt vt + ? vt t r, t f v oh v ol v oh v ol v oh v ol v ol v ol v dd = 4.75 to 5.25v i oh = ?ma i ol = 4ma i oh = ?ma i ol = 4ma i oh = ?ma i ol = 8ma i ol = 3ma i ol = 6ma 180 vss 0.7v dd 2.2 0.7v dd 0 v dd ?0.8 v dd ?0.8 v dd ?0.8 0 0 280 0.5 350 v dd 0.3v dd 0.8 0.3v dd 500 0.4 0.4 0.4 0.4 0.6 mw v v ns v * 1 * 2 * 3 * 4 * 5 * 6 * 7 * 8 * 9 symbol measurement conditions min. typ. max. unit corre- sponding pins cmos input ttl input high level low level hysteresis voltage * 1 all pins * 2 input pins other than * 3 and * 4 * 3 biti, dslb, dsla, datb, data, mute * 4 sda, sclk * 5 all input pins * 6 output pins other than * 7 , * 8 and * 9 * 7 lno, lpo, rpo, rno * 8 bito, ck2m, fram, dato, cci, tx * 9 sda, sclk
?11 cxd2027q/r input leak current output leak current (i 2 c bus) ii iil iih ii ioz v in = v ss or v dd v in = v ss v in = v dd v in = v ss or v dd v in = v ss ?0 ?0 40 ?0 ?0 ?00 100 10 ?40 240 40 ?0 ? ? ? ? ? * 1 * 2 * 3 * 4 * 5 normal input pin with pull-up resistor with pull-down resistor bidirectional pin (during input state) * 1 input pins other than * 2 , * 3 and * 4 * 2 mrst * 3 tst0, tst1, tst2, tst3, tst4, sasl, tst6 * 4 biti, dslb, dsla, datb, data, tst5 * 5 sda, sclk * 6 mcki, m23i * 7 mcki, mcko, m23i, m23o * 8 mcko, m23o [oscillation cell electrical characteristics] (v dd = 5v 0.25v, ta = ?0 to +75?) item symbol measurement conditions min. typ. max. unit corre- sponding pins lvth v ih v il r fb v oh v ol logic threshold value input voltage feedback resistance output voltage v in = v ss or v dd i oh = ?2ma i ol = 12ma 0.7v dd 250k v dd /2 v dd /2 1m 0.3v dd 2.5m v dd /2 v v v v * 6 * 7 * 8 item symbol measurement conditions min. typ. max. unit corre- sponding pins
?12 cxd2027q/r [internal a/d converter characteristics] absolute maximum ratings (ta = 25?) item supply voltage input voltage (analog) input voltage (digital) reference voltage av d ain rb, rt +7.0 av d to av s v dd to v ss av d to av s v v v v symbol ratings unit item supply voltage reference input voltage analog input operating ambient temperature av d , av s l dv s ?av s l rb rt ain topr 4.75 to 5.25 0 to 100 0 to to 3.75 100 to 300 (typ. 200) typ.1.25 ?0 to +75 v mv v mv p-p v ? symbol ratings unit operating conditions amplitude dc level
?13 cxd2027q/r [ac characteristics] (v dd = 5.0v 0.25v, ta = 25?) item alc characteristics carrier regeneration pll pull-in range clock regeneration pll pull-in range deviation from standard input level 200mvp-p pull-in frequency * relative to 5.7272mhz. includes temperature characteristics (?0 to +75?) and supply voltage fluctuation (5%) of vcxo. pull-in frequency * relative to 2.048mhz. includes temperature characteristics (?0 to +75?) and supply voltage fluctuation (5%) of vcxo. ?0 % hz hz conditions min. typ. max. unit * performance guaranteed only when using constants of the recommended oscillation circuit. 22.909088mhz (for carrier regeneration pll) vcxo circuit phaa m23i m23o 100k 2.7 68 390p (ch) hvu359 22k 4.7k 0.01 12p (uj) x'tal vc l : daishinku ag8865c : hitachi hvu359 : matsushita elj-fc series 24.576mhz (for clock regeneration pll) vcxo circuit phab mcki mcko 100k 330 1800p (ch) hvu359 22k 4.7k 0.047 10p (uj) x'tal vc : daishinku ag8865c : hitachi hvu359 upper lower upper lower +750 ?50 +300 ?00
?14 cxd2027q/r (v dd = 5.0v 0.25v, ta = ?0 to +75?, c l = 60pf) item biti set-up time data set-up time datb set-up time biti hold time data hold time datb hold time t su1 t h1 value relative to ck2m fall value relative to ck2m fall 32 0 ns ns symbol conditions min. typ. max. unit (v dd = 5.0v 0.25v, ta = ?0 to +75?, c l = 60pf) item bito delay time dato delay time nsyn delay time fram delay time dtup delay time cc1 delay time aud delay time lrck delay time t d1 t d2 t d3 t d4 t d5 t d6 t d7 t d8 value relative to ck2m fall value relative to bclk fall 17 24 37 23 38 21 28 26 ns ns ns ns ns ns ns ns symbol conditions min. typ. max. unit aaaaa aa aa aa aa tsu1 th1 td1 to td6 td7 to td8 biti, data, datb ck2m ck2m bito, dato, nsyn, fram, dtup, cc1 bclk aud, lrck
?15 cxd2027q/r internal 1-bit dac analog characteristics (fs = 48khz, v dd = 5.0v, ta = 25?, signal frequency = 1khz, measurement band = 4hz to 20khz, b mode) item s/n thd + n output level 90 0.011 1.95 db % v(rms) (eiaj) * 1 (eiaj) * 2 min. typ. max. unit remarks * 1 "a" characteristic weighting filter used * 2 when master clock is 256fs the following circuit is used for analog characteristics measurement. data lch analog rch test disc cxd2027q/r analog circuit analog tester (advantest t7342) cxd2027q/r lno (rno) lpo (rpo) 130k 130k 47p 47p 5.4k 5.4k 4.7k 820p 4.7k 820p 4.7k 1800p 4.7k 4.7k 820p 0.015 22 12k 100 output
?16 cxd2027q/r description of functions alc this detects the fluctuation of the input qpsk modulated signal level and absorbs the fluctuation by controlling a/d vrt. with this function, a signal is output from alco after pwm modulation, and should be fed back to the rt pin after integration. carrier regeneration a 5.727272mhz carrier is regenerated. the input qpsk modulated signal is a/d converted at a sample rate of 22.909088mhz (5.727272mhz 4), and control voltage is generated using that sampling position as phase error data. the control voltage is output from the phaa pin after pwm modulation, and controls vcxo, which consists of an internal oscillation cell and external crystal. clock regeneration this is a pll circuit with 24.576mhz clock. it is 512 fs, for use with the dac. phase comparison is carried out using the regenerated i and q signals and vcxo divided output, and control voltage is generated. after pwm modulation, the control voltage is output from the phab pin, and controls vcxo, which consists of an internal oscillation cell and external crystal. data regeneration a 2.048mhz bit stream is regenerated from the regenerated i and q signals. frame sync and master frame sync correlated detection and competitive counter format is used for sync protection. the number of rear protection is set at three times, and that of front protection is set at 3, 5, 7, or 9 times. also, synchronizing to the master frame can be done when the master frame signal is being sent to the control sign 14th bit. in this case, the number of rear protection is set to 2 times, and that of front protection is set at 7, 9 or 11 times. descramble a superimposed pn signal is removed for bs. also, there is a built-in interface for an external descrambler unit. de-interleave the data interleaved by the built-in 4kbit sram is returned to the correct data array. (63, 56) bch sign error correction this performs (63, 56) bch sign error correction. error capability is 1 error correction, 2 errors detection. range bit bch sign error correction this performs (7, 3) bch sign error correction. error capability is 1 error correction, 2 errors detection. when there are 2 errors, the previous value is held.
?17 cxd2027q/r control sign integration detection and 8th range bit integration detection integration detection is carried out in units of 15 frames. when a match of 12/15 or more is obtained, a defined control sign is detected. however, updating is every 18 frames. when a match of 12/15 or more is not obtained, the previous value is held. further, synchronizing to the master frame can be done when the master frame signal is being sent to the control sign 14th bit. after integration detection, the control sign and range bit can be read by the i 2 c bus. 10 ? 14 bit data expansion during a mode, the instantaneously compressed 10 bits of audio data are expanded to 14 bits according to the range expansion rule. the lower bits of data are fixed at a set value during expansion, and the data is treated as 16 bits. upper bit majority detection during b mode, this carries out upper bit majority detection and protects the upper bits. mute signal generation this performs muting by the external mute signal and internal logic, and also generates a mute signal according to the mute setting from the i 2 c bus. audio data interpolation this receives the bit error detection signal and interpolation indication signal from majority detection, and then carries out the average value interpolation or the previous value hold. clock generation for d/a converter this generates the clock for the dac. digital filter (df) and de-emphasis a 2ch 1-bit dac with 2nd-order ? format noise shaper of quadruple oversampling filter is built in. the output format is differential. de-emphasis function corresponding to the mode is also built in. audio interface one of the following three output formats can be selected. 1) sony: bit clock 32 fs/ msb first/ 16 bits (for built-in d/a converter) 2) iis: sony format 1 bclk delay 3) bit clock 64fs / msb first / 16 bits rearward truncation digital interface conforms to the following digital audio interface format: type ii form i (for consumer digital audio equipment) ? 2 c bus interface control by microcomputer is carried out by the i 2 c bus i/f. the slave address can be switched by controlling sasl; for low: d4, for high: d6.
?18 cxd2027q/r output channel selection the output channels provided are analog output for built-in d/a converter lch/rch, one output system for external d/a audio output and one for digital audio output. channel selection can be done easily through the i 2 c bus. unused channels can be suppressed using the i 2 c bus. audio output selection mode selection can be carried out via the i 2 c bus. zero cross muting the i 2 c bus can be used for zero cross muting. when a mute signal is input, muting is not carried out until zero cross conditions are satisfied for 1 frame. if these conditions are not met for 1 frame, muting is forced at the next frame. zero cross mute cancel is performed in frame units. the conditions for zero cross are a change in audio data msb, or when audio data value is between 00ffh and ff00h. description of mute function a signal is treated as a mute signal in the following cases: 1) when asynchronous 2) control sign 7th bit (non-broadcast flag) or 16th bit (audio suppression flag) is high 3) 8th range bit (audio chargeable flag) is high (however, only channel for high) 4) number of double error flags goes over a certain th level (error frequency detection mute) 5) audio carrier (5.7272mhz) can not be detected 6) an i 2 c bus mute flag is up 7) for other than audio 1. asynchronous flag mute muting is applied when an asynchronous state exists. also, the number of front sync protection can be changed among 3, 5, 7 or 9 times by the i 2 c bus, so the conditions for asynchronous flag muting can be changed. 2. muting by control sign 7th and 16th bits the control sign 7th bit is a flag indicating broadcast or non-broadcast. if this bit is high, muting is applied. also, the i 2 c bus can be used so that this bit does not apply muting. the control sign 16th bit audio suppression flag is used when broadcast channels are switched and when transmission modes are switched. both use the value after integration detection. 3. chargeable flag detection mute the 8th range bit indicates if audio data is for a chargeable broadcast or not. for a chargeable broadcast, a flag ("h") goes up in that bit's position. when this bit is high, the broadcast is detected as chargeable and muting is applied. further, the i 2 c bus can be used for each channel so that this bit does not apply muting. the value after every 18 frames of integration detection is used.
?19 cxd2027q/r 4. error frequency detection mute muting is applied after bch (63, 56) sign error correction is executed for every 64 data, when the number of double error detection flags goes over a certain th (threshold value) level during a certain number of frames. also, the i 2 c bus can be used so that muting is not applied. the setting values are indicated below. number of frames: 128, 256, 512, 1024 up to 32 double errors can be detected in one frame, so 1/16, 1/8, 1/4 and 1/2 of the maximum detections for each frame number are set as the th levels. therefore, there are 16 possible combinations, and the value is set by the i 2 c bus. the th level for muting cancel is half of the th value when muting is applied; in other words, 1/32, 1/16, 1/8 and 1/4, respectively. 5. carrier detection mute when the bs broadcast audio carrier frequency of 5.7272mhz can not be detected by the psk demodulator unit, muting is applied. also, the i 2 c bus can be used so that muting is not applied. 6. i 2 c bus muting the i 2 c bus can apply forced muting to analog and aud outputs. tx output is locked to analog output. 7. muting other than audio muting is done for other than audio mode when the control sign 2nd and 3rd, or 4th and 5th bits are "h, h".
?20 cxd2027q/r external descramble i/f circuit example coatec and skyport units can be connected simultaneously. bito bstmi biti bstmo dslb rgnd dato dati datb dsdo data dati dsla dasl dato cxd2027q/r coatec unit skyport unit unit connection daslc i 2 c bus register dsla 0 0 1 1 dslb 0 1 0 1 descramble format coatec, skyport * skyport coatec internal * the coatec unit and skyport unit can be connected simultaneously. however, use the i 2 c bus to set daslc at high when turning off the coatec unit power supply.
?21 cxd2027q/r bit stream signal interface data interface after bch error correction bito is output at falling sync. 2048 1 2 3 4 2047 2048 1 2 ck2m bito dato is output at falling sync. 2048 1 2 3 4 2047 2048 1 2 ck2m dato fram 1ms 1 frame examples of error detection countermeasures for low c/n control sign and chargeable flag integration detection when c/n is low, nsyn frequently goes high level (asynchronous state). in this case, problems such as wrong display or wrong detection of control sign 7th bit "broadcast/non- broadcast" flag may occur due to incorrect integration detection. this can be improved using the microcomputer software shown below. integration detection result can be updated only when nsyn is low level. detection results of this ic are read by the standard trigger of the microcomputer, and if the result values match for 5 to 6 times continuously, the detection result is taken as an update for the system. it is also possible to update the integration detection result by the continuous matching of 7 times or more. however, standard trigger cycle of the microcomputer must be set about 18ms. 18ms 123456 nsyn control sign,chargeable flag (ic) control sign,chargeable flag (microcomputer) ? integration detection results standard trigger (microcomputer)
?22 cxd2027q/r description of i 2 c bus the i 2 c bus is a bidirectional serial bus system developed by philips. it can transmit and receive data between multiple devices using two lines, sclk (serial clock) and sda (serial data). this lsi has a built-in i 2 c bus interface circuit and is compatible with slave receiver and slave transmitter operation modes. for the transfer configuration, both receiver mode and transmitter mode have sub-addresses. receiver mode the first byte is the slave address, the second byte is the sub-address, and data is read at the third byte and after. continuous data reading is also possible. after transmission of the first byte, the sub-address is made (+1) automatically. transmitter mode the first byte is the slave address, and data is sent at the second byte and after. continuous data output is also possible. after transmission of the first byte, the sub-address is made (+1) automatically. when there is no verification answer from the master, the sda line is released. to read data, the sub-address for the data to be read is written in receiver mode, then the data is read in transmitter mode. the sda line is released for initial reset, so the bus is not occupied. also, even if the ic supply voltage falls to 0v, the bus is not occupied. nonetheless, please keep within the absolute maximum ratings. this bus is compatible not only with standard mode (maximum 100kbit/s) but with high speed mode (maximum 400kbit/s) as well.
?23 cxd2027q/r specifications data write (receiver mode) to 7654321 slam wm subm as datam as as sm 0 76543210 1 76543210 1 1 to datam as datam as p 76543210 1 1 76543210 to 7654321 slam wm subm as as sm 0 76543210 1 1 to datas slam am as rm srm datas xam p 76543210 7654321 1 1 01 87654321 data read (receiver mode & transmitter mode) symbol * m * s s sr p sla sub data w r a xa from master to slave from slave to master start condition start condition stop condition slave address sub address data 0 : write master ? slave 1 : read slave ? master clock pulse for acknowledgement (sda: l) acknowledgement none (sda:h) description
?24 cxd2027q/r i 2 c bus control table sasl slave address l d4 h d6 r/w wr rd sub- address 00'h 01'h 02'h 03'h 04'h 05'h 06'h 07'h 00'h 01'h 02'h a1s1 busmt1 otstp1 daslc (tsb0) rgof1 cc1 cc9 (l) a1s2 busmt2 otstp2 c1sl (tsb1) rgof2 cc2 cc10 (l) a1s3 amute otstp3 lrsl xeoff rgof3 cc3 cc11 (l) sig otstp4 iis xinh rgof4 cc4 cc12 (l) a2s1 dos1 mtof0 nf1 blfs c2 pi1 otsl cc5 cc13 rg81 a2s2 dos2 mtof1 nf2 fpcc c10 pi2 mfram cc6 cc14 rg82 a2s3 dos3 mtof2 th1 fpcb xprt nr (test2) cc7 cc15 rg83 mtof3 th2 (test1) domu (test3) cc8 cc16 rg84 msb bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 data lsb blanks : data not related to internal logic. ( ) : data for testing. fix to the default value. (l) : low is output. msb, lsb : data is transmitted with msb first. default data (default value of internal register after master reset) w wr sub- address 00'h 01'h 02'h 03'h 04'h 05'h 06'h 07'h 0 0 0 0 (0) 1 1 0 0 0 (0) 1 0 1 0 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 0 0 1 0 1 0 0 (0) 1 1 (0) 0 (0) msb bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 data lsb ( ) : always fix to the default value.
?25 cxd2027q/r bus setting values for audio output selection sub-address 00'h 00000000'b bit no. bit7 bit6 bit5 bit3 bit2 bit1 a1s1 a1s2 a1s3 a2s1 a2s2 a2s3 audio output mode selection when using built-in df/dac audio output mode selection when using external df/dac name description applications a1s1 a2s1 dos1 0 1 x 0 0 0 1 1 1 x x x 0 1 x tv independent main + sub main sub main + sub main sub main + sub main sub main main main tv independent tv independent a mode a mode stereo 2ch mono 1ch mono b mode b mode a mode b mode a1s2 a2s2 dos2 x x x 1 0 0 1 0 0 1 0 0 x x x a1s3 a2s3 dos3 x x x x 0 1 x 0 1 x 0 1 x x x sub-address 01'h 00000001'b bit no. bit3 bit2 bit1 dos1 dos2 dos3 output mode selection when using digital interface name description same setting method as for a1s1, a1s2 and a1s3
?26 cxd2027q/r muting-related bus setting values sub-address 02'h 00000010'b bit no. bit7 bit6 bit3 bit2 bit1 bit0 busmt1 busmt2 mtof0 mtof1 mtof2 mtof3 audio data mute when using built-in df/dac audio data mute when using external df/dac carrier detection mute non-broadcast flag mute error occurrence frequency mute external mute (exmu) on on on on on on off off off off off off name description h l sub-address 03'h 00000011'b bit no. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 otstp1 otstp2 otstp3 otstp4 nf1 nf2 th1 th2 signal suppression for external df/dac (aud, lrck, bclk) signal suppression for external descramble (ck2m, fram, dato) control sign output suppression (nsyn, ccup, cc1) built-in df/dac operation / non-operation selection error occurrence frequency mute setting (number of frames) error occurrence frequency mute setting (threshold value) non- operation non- operation non- operation non- operation operation operation operation operation name description h l bit3 nf1 0 0 1 1 bit2 nf2 0 1 0 1 number of frames 128 256 512 1024 bit1 th1 0 0 1 1 bit0 th2 0 1 0 1 threshold value mute * 1 1/2 1/4 1/8 1/16 cancel * 2 1/4 1/8 1/16 1/32 * 1 mute when over this value * 2 mute cancel when below this value
?27 cxd2027q/r bit no. bit7 bit6 bit5 bit4 bit2 bit1 bit0 rgof1 rgof2 rgof3 rgof4 mfram test2 test3 audio 1ch mute audio 2ch mute audio 3ch mute audio 4ch mute master frame sync processing for testing (fix to low) for testing (fix to low) on on on on off off off off off on name description h l bus setting values for chargeable flag mute sub-address 07'h 00000111'b bit no. bit4 sig signal polarity selection for external descramble i/f inverted positive name description h l bus setting values for external i/f, etc. sub-address 02'h 00000010'b corresponding input pins : biti, data, datb corresponding output pins : ck2m, dato, fram
?28 cxd2027q/r sub-address 04'h 00000100'b bit no. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 daslc c1sl lrsl iis blfs fpcc fpcb test1 external descramble i/f control cc1 (control sign 1st bit) output polarity inversion lrck polarity inversion audio output format switching selection of the number of front protection for frame sync protection and master frame syncprotection selection for testing (fix to low) inverted inverted positive positive refer to page 20. name description h l bit4 iis 1 1 0 0 bit3 blfs 1 0 1 0 format prohibited 2) iis 3) 64fs 1) sony bit2 fpcc 1 1 0 0 bit1 fpcb 1 0 1 0 the number of frame sync front protection 3 5 7 9 bit no. bit3 otsl dtup pin output signal switching ded ccup name description h l sub-address 07'h 00000111'b bit no. bit3 bit2 bit1 bit0 c2 c10 xprt domu digital copy allowed/prohibited selection channel status 10th bit parity inversion selection for digital interface mute for digital interface (tx is dc low) allowed general transmission error on prohibited bs normal off name description h l digital i/f bus setting values sub-address 05'h 00000101'b the number of master frame sync front protection 7 9 11 11
?29 cxd2027q/r df and d/a converter-related bus setting values write register sub-address 06'h 00000110'b bit no. bit7 bit6 bit5 bit4 bit3 bit2 bit1 tsb0 tsb1 xeoff xinh pi1 pi2 nr for testing (normally set to low regardless of input data) digital de-emphasis selection dc dither selection dc dither phase control rch dc dither phase control lch modulation nr on on inverted inverted on off off positive positive off name description h l control sign bit reading after integration correction sub-address 00'h 00010000'b bit no. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cc1 cc2 cc3 cc4 cc5 cc6 cc7 cc8 control sign 1st bit control sign 2nd bit control sign 3rd bit control sign 4th bit control sign 5th bit control sign 6th bit control sign 7th bit control sign 8th bit mode selection tv audio additional audio name description sub-address 01'h 00010001'b bit no. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cc9 cc10 cc11 cc12 cc13 cc14 cc15 cc16 control sign 9th bit control sign 10th bit control sign 11th bit control sign 12th bit control sign 13th bit control sign 14th bit control sign 15th bit control sign 16th bit expansion bits video scramble existent/non-existent master frame sync flag h: asynchronous, l: synchronous data suppression audio output suppression name description suppression backup broadcast identification expansion bit
?30 cxd2027q/r range 8th bit read after integration correction sub-address 02'h 00010010'b bit no. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rg81 rg82 rg83 rg84 low level fixed output range 8th bit (chargeable flag) 1ch range 8th bit (chargeable flag) 2ch range 8th bit (chargeable flag) 3ch range 8th bit (chargeable flag) 4ch name description
?31 cxd2027q/r application circuit cxd2027r 61 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 62 nc10 v dd 5 m23o m23i phaa alco v ss 9 nc12 tst7 rt nc13 adin advd advs rb gr tst0 nc14 nc15 nc11 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2 nc0 v ss 0 bito dslb dsla datb data v dd 0 ck2m fram dato cc1 biti tx tst2 tst3 tst4 tst5 nc1 mrst 40 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 39 nc7 sasl v ss 6 v ss 5 rno nc5 v dd 2 rpo v ss 4 tst1 v ss 3 lpo v dd 1 nc4 lno v ss 2 v ss 1 nc3 nc6 nc2 60 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 59 nc9 phab mdki mcko v ss 8 mute tst8 v ss 7 sclk sda v dd 3 nsyn dtup f256 bclk lrck aud tst6 nc8 v dd 4 100k 330 24mhz 10p: ch 4.7k 22k 0.047/16v hvu359trf d24 + 5v 0.1 47/16v 4.7k d24 + 5v 4.7k 220 2 nsyn d23 + 5v 47 16v 0.1 23mhz 12p: ch 68 2.7 390p: ch 0.01 hvu359trf 100k 22k 4.7k 47 16v 0.1 dad + 5v 47/16v 1 3 3 1 2 2 5.6k 22k 2sc2712 (h fe 3 200) 2sa1162 2200p 12k 12k 0.01 1000p bpf 10k d24 + 5v sw rest 100 d24 + 5v 5.6k 5 coatec skyport 8 bito 7 biti 6 dslb 5 dato 4 datb 3 ck2m 2 fram 1 7 dato 6 data 5 dsla 4 ck2m 3 fram 2 cc1 1 100 6 dad + 5v d23 + 5v d24 + 5v aout + 12v a + 5v a + 5v 47/16v 9.1k 8.2k 9.1k 8.2k 120p: ch 9.1k 8.2k 9.1k 8.2k 150p : ch 6.8k 2200p: ch 2 3 1 8 4 njm4580e 30k 30k 2200p: ch 6.8k 150p: ch 15k 0.1 47/16v 2200p: ch 6.8k 150p: ch 15k 2 3 1 8 4 150p: ch 6.8k 2200p: ch njm4580e 30k 30k 6 5 7 njm4580e 1500p: ch 680 0.027 680 680 0.01 : ch 47/16v output r ch 6 5 7 njm4580e 1500p: ch 680 0.027 680 680 0.01 : ch 47/16v output l ch d24 + 5v 0.01 47/16v 5.6k 100 tx bito 100 4 1 f256 2 bclk 3 lrck 4 aud 5 100 5 d_out 1 scl 2 sda 3 i 2 c analog input aout + 12v 1800p: ch 120p: ch 120p: ch 120p: ch 0.1 0.1 5.6k d24 + 5v buffer 0.1 0.1 note 1) circuit connection and constants are the same for the cxd2027q. note 2) this circuit example shows digital de-emphasis off. the analog de-emphasis circuit is included in the external circuit connected to the built-in dac. application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to the same.
?32 cxd2027q/r package outline unit: mm cxd2027q cxd2027r sony code eiaj code jedec code 23.9??.4 20.0?.1 1.0 0.4 ?0.1 + 0.15 14.00.1 1 19 20 32 33 51 52 64 0.15 ?0.05 + 0.1 2.75 ?0.15 16.3 0.1 ?0.05 + 0.2 0.8 0.2 m 0.12 0.15 +?.4 17.9??.4 +0.4 + 0.35 64pin qfp(plastic) qfp?4p?01 * qfp064??420 package material lead treatment lead material package weight epoxy resin solder/palladium copper /42 alloy package structure plating 1.5g sony code eiaj code jedec code package material lead treatment lead material package weight epoxy / phenol resin solder plating 42 alloy package structure 14.0 0.2 * 12.0 0.1 (0.22) 60 41 40 21 20 80 61 1 0.5 0.08 0.18 ?0.03 + 0.08 a 1.5 ?0.1 + 0.2 0.127 ?0.02 + 0.05 0.5 0.2 (13.0) 0.1 0.1 0.5 0.2 0?to 10 detail a 80pin lqfp (plastic) 0.5g lqfp-80p-l01 * qfp080-p-1212-a 0.1 note: dimension * ?does not include mold protrusion.

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